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| TDA7572 200W mono bridge PWM amplifier with built-in step-up converter Preliminary Data Features Input stage and gain compressor Over-modulation protection and current limiting Modulator DAC Step-up Mode control Diagnostics / safety Power control Broad operating voltage is supported, allowing operation from both 14V and 42V automotive power buses, as well as from split supplies for consumer electronics use. A current mode control boost converter controller is provided to allow high power operation in a 14V environment. Turn-on and turn-off transients are minimized by soft muting/unmuting and careful control of offsets within the IC. Digital Audio input is supported by an integrated one channel DAC. Sophisticated diagnostics and protection provide fault reporting via I2C and power shutdown for safety related faults. TDA7572 is packaged in a HiQUAD-64 package. HiQUAD-64 Description TDA7572 is a highly integrated, highly versatile, semi-custom IC switch mode audio amplifier. It integrates audio signal processing and power amplification tailored for standalone remote bass box applications, while providing versatility for full bandwidth operation in either automotive or consumer audio environments. It's configured as one full bridge channel, using two clocked PWM modulators driving external, complementary FET's. Table 1. Device summary Order code TDA7572 Package HiQUAD-64 Packing Tray September 2007 Rev 1 1/64 www.st.com 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents TDA7572 Contents 1 2 3 4 Detailed features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 4.2 4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 Operating voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Gate drive and output stage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4 Voltage booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 Digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I/O pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Op. amp. cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 I2C and mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 5.2 5.3 5.4 5.5 5.6 Input control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Faults 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Faults 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Modulator register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Testing register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 Input stage and gain compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2/64 TDA7572 Contents 6.2 Gain compressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.1 6.2.2 Setting in I2C bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Soft-mute function, without pre-limiter . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 7.2 FET drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ANTI-POP shunt driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 9 10 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Step-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.1 Faults during operation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.7 10.1.8 DC offset across the speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 External temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Output clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Output over-current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Power supply overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Faults during power-up: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11 12 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Under voltage lock out (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.1 12.2 12.3 VSP-UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 V14 - UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SVR - UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13 Start-up procedures, modulator turn-on after a tristate condition. . . 56 13.1 13.2 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Tristate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 14.1 14.2 Single supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Split supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3/64 Contents TDA7572 14.3 THD+N step-up on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 15 16 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4/64 TDA7572 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin list by argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin list by pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Gate drive and output stage control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Voltage booster. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I/O pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Op. amp. cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Analog operating characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power-up mode control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 I2C chip address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Input control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Faults 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Faults 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Modulator register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Testing register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Distortion versus gain step size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Sets the maximum release rate of the gain compressor. . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Sets the maximum attack rate of the gain compressor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Attack/release rate and gain compression effort selection . . . . . . . . . . . . . . . . . . . . . . . . . 39 PWMClock table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5/64 List of figures TDA7572 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mute by external command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Mute by I2C bus command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Modulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Current sourced by the shunt pin in NO I2Cbus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DAC circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Two interpolator structure diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I2S format diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Step-up application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Threshold of current limiting diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Single supply evaluation board schematic.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Single supply evaluation PCB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Split supply evaluation board schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Split supply evaluation PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 THD+N step-up on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 HiQUAD-64 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6/64 TDA7572 Detailed features 1 Detailed features Input Stage and Gain Compressor - Differential, high CMRR, analog input - Programmable input attenuation/gain to support up to four drive levels - Noiseless Gain compression of up to 16 dB with programmable attack and decay. - Compressor controlled by monitoring estimated THD - Soft mute / un-mute for pop control Over-modulation Protection and Current Limiting - Adaptive pulse injection prevents missing pulses due to over modulation which maximizes useful output swing. - Programmable current limiting based on FET VDS Modulator - Optimized for low distortion at low switching frequency (approximation 110KHz) - Dual Clocked PWM modulators for 3 state switching - External gain control / internal integrator components - Controls 4 external FETS with switching optimized for low EMI - Oscillation frequency selectable by I2C - Anti-pop shunt driver DAC - 18bit, mono - I2S inputs 38-48KHz, 96KHz, 192 KHz - Hybrid architecture, area optimized for Bass - Full bandwidth supported by off loading the interpolator function - Synchronization with modulator Step-Up - On board STEP-UP step up converter, synchronized to the modulator frequency - Drives external NFET switch - Externally compensated - Soft start and current limiting Mode Control - Critical modes controllable by mode pins for bus-less operation - I2C provides additional mode control Diagnostics / Safety - Offset, short, open, overcurrent, over temperature - I2C used to report errors, and for configuration control - Faults pin used to report errors in bus-less environment - Clipping reported at a separate pin - Abnormal supply current detection disables input power for fail safe operation - Output current limiting - Power control - Latching control of an external PMOS power switch for safety related faults. - Power is switched off for safety related faults of abnormal supply current, excessive internal or external temperature, or persistent output stage over-current that fails to be controlled by the pulse-by-pulse current limiting method 7/64 Interface description TDA7572 2 Interface description I2C bus and mode control pins are use to control operation. Default values of all the operating modes are deterministic, some of these values are intrinsic to the IC and some are determined by configurations pins. The configuration pins are read at power-up and copied into registers, which may later be modified using the I2C bus, if one is present. This allows varied operation in an environment where NOI2C bus is present, while allowing full control and override of pin programmed modes when used with I2C. Figure 1. Block diagram SDA / SCR_ENB SCL / InputLevel1 PLL / InLevel0 BSTVSource BSTVSense WS / CLIP_L V14Sense BSTGate CSense DACM DACP VM2.5 DGND MOD1 VP2.5 V14 VDIG DC/DC Converter Regulators DAC PWM Channel 1 Pulse Inj . LSD1SourceSensing LSD1GateDrive LSD1GateSensing ISSENP ISSENM Mode 0 Mode 1 Automute Voltage Setting Mute Vs/2 or SVR I2C data / attack sel. I2C clock Addr 0 / Fault / CLIP_L Addr1 / CompEnable NTC ShuntDrive +Vs current protection Integrator HB1OutFilter HB1Out ILimit threshold Mode sel . and Mute LOGIC Drivers Prot. & supply HSD1GateSensing HSD1GateDrive HSD1SourceSensing VSP_Pow1 I2Cbus UVLO PWM Channel 2 Pulse Inj . Integrator HSD2SourceSensing HSD2GateDrive HSD2GateSensing Thermal management VSP_Pow2 HB2Out Diff -to-S.E. Compressor and Limiter Channel 1 LSD2OutFilter Drivers TestC Iset Diagnostics + clipdet Controls and Diagnostics LSD2GateSensing LSD2GateDrive LSD2SourceSensing -1 Protections Oscillators INP CLKin -out DITH -sel OscOut AOUT InvOut InvIn INM VSM1,2,3,4 MOD2 AC00014 8/64 TDA7572 Pins description 3 Pins description Figure 2. Pins connection (top view) ADDR1/CompEnable ADDR0/Fault/Clip_L I2CDATA/AttackSel IlimitThresh AutoMuteVSetting MUTE_L Mode0 I2CLK Mode1 64 63 62 61 60 59 Iset TestC LSD2SS LSD2GD LSD2GS HB2OutFilt HB2Out HSD2GS HSD2GD HSD2SS VSP_POW2 VSP_POW1 HSD1SS HSD1GD HSD1GS HB1Out HB1OutFilt LSD1GS LSD1GD LSD1SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VSM2 BSTGate BSTSource CSense V14Sense V14 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 27 28 29 30 31 32 VSM1 BSTVSense ISSENM ISSENP DAC2 DAC1 SVR VM2.5 VDIG DGND NTC SCL/InLevel1 WS/Clip_L SDA/SCR_ENB PLL/InLevel10 ShuntDriver DITH CLKIN/Out OscOut MOD2 MOD1 InvOut InvIn AOUT INP INM VSM3 VP2.5 AC00013 VSM4 9/64 Pins description Table 2. Pin # On/Off Circuitry 11 53 51 50 49 52 55 54 57 56 VSP_POW2 VP2.5 VM2.5 VDIG DGND SVR Mode0 Mode1 MUTE_L AutoMuteVSetting TDA7572 Pin list by argument Pin name Description Positive supply power for low power, non gate-drive functions with a separate bonding to power the gate drive of modulator two +2.5V analog supply output -2.5 V analog supply output 5V logic supply decoupling Digital gnd Vs/2 analog reference filter capacitor. Reference for input stage. Mode control bit0, selects standby/normal/ I2C/diagnostic operation Mode control bit1, selects standby/normal/ I2C/diagnostic operation Mute input and / or timing cap, assertion level low Auto-mute Voltage Setting Input/ Gain Compressor 34 33 35 INP INM AOUT Non inverting audio input Inverting audio input Compressed Audio Output Input Stage gain selection - see PLL pin in DAC Section 8 Compressor attack/decay select - see I2C data pin in DAC Section 8 Inverter 36 37 Modulator 64 32 38 20 19 18 17 16 15 14 13 12 IlimitThresh LVLSFT MOD1 LSD1SS LSD1GD LSD1GS HB1OutFilt HB1Out HSD1GS HSD1GD HSD1SS VSP_POW1 Output stage Current Limiting trip voltage set point Gain program pin for SVR to HVCC level shifting Modulator1 Inverting / Summing node Lowside1 Source Sensing Lowside1 Gate Drive Lowside1 Gate sense Half bridge1 post-LC filter - for diagnostics Half-bridge1 output, HSD 1 drain sense, LSD1 Drain Sense Highside1 Gate sense Highside1 Gate Drive Highside1 Source sense Positive supply voltage connection for gate drive circuitry InvIn InvOut Inverter input Inverter Output 10/64 TDA7572 Table 2. Pin # 39 10 9 8 7 6 5 4 3 27 26 58 59 43 DC-DC 28 22 21 23 24 25 Oscillator 41 42 40 CLKIN/Out DITH OscOut Clock input Dither capacitor Oscillator output BSTVSense BSTSource BSTGate CSense V14Sense V14 Voltage feedback input for Voltage Booster Boost Converter NFET Source Boost Converter NFET gate drive Pins description Pin list by argument (continued) Pin name MOD2 HSD2SS HSD2GD HSD2GS HB2Out HB2OutFilt LSD2GS LSD2GD LSD2SS VSM1 VSM2 VSM3 VSM4 ShuntDriver Description Modulator2 Inverting / Summing node Highside2 Source sense Highside2 Gate Drive Highside2 Gate sense Half-bridge2 output, HSD 1 drain sense, LSD1 Drain Sense Half bridge2 post-LC filter - for diagnostics Lowside2 Gate sense Lowside2 Gate Drive Lowside2 Source Sense Die tab connection to lowest supply voltage - gnd for single ended supplies, negative supply for split supplies Die tab connection to lowest supply voltage - gnd for single ended supplies, negative supply for split supplies Die tab connection to lowest supply voltage - gnd for single ended supplies, negative supply for split supplies Die tab connection to lowest supply voltage - gnd for single ended supplies, negative supply for split supplies Shunt Driver Inverting input for Booster Current Sensing and Digital Test Enable (operating when is more then about 3V under the V14 pin level) Non-inverting input for Booster Current Sensing Power for Boost converter gate drive and Output LSD's Diagnostics / Bus 62 63 I2CDATA/AttackSel I2CLK I2C data (I2C mode) Compressor aggressiveness selection (non-bus mode) I2C Clock 11/64 Pins description Table 2. Pin # TDA7572 Pin list by argument (continued) Pin name I2 2 Description C address set (I C mode) Fault output in non bus mode (non-bus mode) Clipping indicator, assertion level low, (when DAC is enabled) 61 ADDR0/Fault/Clip_L 60 48 2 1 30 29 DAC 46 45 47 44 31 32 ADDR1/CompEnable NTC TestC ISet ISSENP ISSENM I2C address set (I2C mode) Compressor Enable/disable (non-bus mode) Connection for NTC thermistor Test cap used to generate the slow current pulses Program pin for current level used in Short/Open test Supply non-inverting current sense Supply inverting current sense WS / Clip_L SDA/SCR_ENB SCL/ InLevel1 PLL/InLevel0 DAC2 DAC1 I2S Word select / Clipping indicator, assertion level low (non-DAC mode) I2C serial data / SCR ENABLE (non DAC mode) I2C serial data bit clock/ Input Level selection bit1 (non-DAC mode) DAC clock PLL filter/ Input Level selection bit 0 (non-DAC mode) DAC output voltage p DAC output voltage n Table 3. Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin list by pin Pin name Iset TestC LSD2SS LSD2GD LSD2GS HB2OutFilt HB2Out HSD2GS HSD2GD HSD2SS VSP_POW2 VSP_POW1 HSD1SS HSD1GD HSD1GS Description Program pin for current level used in Short/Open test Test cap used to generate the slow current pulses Lowside2 Source Sense Lowside2 Gate Drive Lowside2 Gate sense Half bridge2 post-LC filter - for diagnostics Half-bridge2 output, HSD 1 drain sense, LSD1 Drain Sense Highside2 Gate sense Highside2 Gate Drive Highside2 Source sense Positive supply power for low power, non gate-drive functions with a separate bonding to power the gate drive of modulator two Positive supply voltage connection for gate drive circuitry Highside1 Source sense Highside1 Gate Drive Highside1 Gate sense 12/64 TDA7572 Table 3. Pin # 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pins description Pin list by pin (continued) Pin name HB1Out HB1OutFilt LSD1GS LSD1GD LSD1SS BSTGate BSTSource CSense V14Sense V14 VSM2 VSM1 BSTVSense ISSENM ISSENP DAC2 DAC1 INM INP AOUT InvIn InvOut MOD1 MOD2 OscOut CLKIN/Out DITH ShuntDriver PLL/InLevel0 SDA/SCR_ENB WS / Clip_L SCL/ InLevel1 NTC Description Half-bridge1 output, HSD 1 drain sense, LSD1 Drain Sense Half bridge1 post-LC filter - for diagnostics Lowside1 Gate sense Lowside1 Gate Drive Lowside1 Source Sensing Boost Converter NFET gate drive Boost Converter NFET Source Inverting input for Booster Current Sensing and Digital Test Enable (operating when is more then about 3V under the V14 pin level) Non-inverting input for Booster Current Sensing Power for Boost converter gate drive and Output LSD's Die tab connection to lowest supply voltage - gnd for single ended supplies, negative supply for split supplies Die tab connection to lowest supply voltage - gnd for single ended supplies, negative supply for split supplies Voltage feedback input for Voltage Booster Supply inverting current sense Supply non-inverting current sense Half VCC (VSP- VSM)/2 Used for output stage reference. Gain program pin for SVR to HVCC level shifting Inverting audio input Non inverting audio input Compressed Audio Output Inverter input Inverter Output Modulator1 Inverting / Summing node Modulator2 Inverting / Summing node Oscillator output Clock input Dither capacitor Shunt Driver DAC clock PLL filter/ Input Level selection bit 0 (non-DAC mode) I2C serial data / SCR ENABLE (non DAC mode) I2S Word select / Clipping indicator, assertion level low (non-DAC mode) I2C serial data bit clock/ Input Level selection bit1 (non-DAC mode) Connection for NTC thermistor 13/64 Pins description Table 3. Pin # 49 50 51 52 53 54 55 56 57 58 59 60 TDA7572 Pin list by pin (continued) Pin name DGND VDIG VM2.5 SVR VP2.5 Mode1 Mode0 AutoMuteVSetting MUTE_L VSM3 VSM4 ADDR1/CompEnable GND logic supply decoupling 5V logic supply decoupling -2.5 V analog supply output Vs/2 analog reference filter capacitor. Reference for input stage. +2.5 V analog supply output Mode control bit1, selects standby/normal/I2C/diagnostic operation Mode control bit0, selects standby/normal/ I2C/diagnostic operation Auto-mute Voltage Setting Mute input and / or timing cap, assertion level low Die tab connection to lowest supply voltage - gnd for single ended supplies, negative supply for split supplies Die tab connection to lowest supply voltage - gnd for single ended supplies, negative supply for split supplies I2C address set (I2C mode) Compressor Enable/disable (non-bus mode) I2C address set (I2C mode) Fault output in non bus mode (non-bus mode) Clipping indicator, assertion level low, (when DAC is enabled) I2C data (I2C mode) Compressor aggressiveness selection (non-bus mode) I2C Clock Output stage Current Limiting trip voltage setpoint Description 61 ADDR0/Fault/Clip_L 62 63 64 I2CDATA/AttackSel I2CLK IlimitThresh 14/64 TDA7572 Electrical specifications 4 4.1 Table 4. Symbol VSP Vpeak VDATA TJ TStg PDMAX Electrical specifications Absolute maximum ratings Absolute maximum ratings Parameters Supply voltage Peak supply voltage Data pin voltage Junction temperature Storage temperature Power Dissipation Any operating condition For thermal budgeting (VS+ - VS-) time 50ms w.r.t Dgnd VS--0.6 -40 -55 Test Conditions Min. VSM -0.6 Max. VSM +58 68 6V 150 150 2.5 Units V V V C C W 4.2 Thermal data Table 5. Symbol RTh j-case Thermal data Parameters Thermal resistance junction to case Value 3 Units C/W 4.3 Electrical characteristics Unless otherwise specified, all ratings below are for -40C < TJ < 125C, VSP = 42V, VSM = 0V and the application circuit of Figure 12. Operation of the IC above this junction temperature will continue without audible artifacts until thermal shutdown, but these parameters are not guaranteed to be within the specifications below. FPWM=110KHz, Booster not enabled. 4.3.1 Table 6. Symbol Operating voltage and current Operating voltage and current Parameters Test conditions Normal operation without audible defects required Single ended supply 42V configuration, VSM=0 Normal operation without audible defects required Single ended supply 14V configuration, VSM=0 Min. Typ. Max. Units VSP42 Operating voltage 42V automotive range 30 42 58 V VSP14 Operating voltage 14.4V automotive range 9 14.4 15/64 Electrical specifications Table 6. Symbol TDA7572 Operating voltage and current (continued) Parameters Test conditions Normal operation required Split supply application configuration, VSM Operating voltage VSP VSM split supply rails 8 48 58 V VSP>VSVR+4 Istdby Stand-by current IC in standby, Mode0, and Mode1 low Vs = 42V V14 Outputs tristated Booster not running, VSP Fpwm = nominal V14 MUTE asserted, VSP 20 13 15 10 50 at T = 25C 10 at T = 85C 20 A Itristate Tristate current mA 25 mA IMUTE Mute mode current 4.3.2 Table 7. Symbol Under voltage lockout Under voltage lockout Parameters AutomuteVSetting pin Test conditions Voltage limit respect to the SVR pin Allowed voltage range on Automute pin Min. Typ. Max. Units VLimAM VSP UVLO voltage limit 0.5 2.1 V VAM Auto-mute supply voltage VSP Auto-tristate supply voltage VSP negative slope Auto-tristate supply voltage VSP positive slope Mute is forced if VSP-VSVR or VSVR-VSM is less than this value VautomuteVSetting-VSVR=VVSVR The IC is set in tristate if VSP-VSM is less than this value Vautomute VSetting-VSVR=VVSVR The IC is set out from tristate if VSP-VSM is higher than this value Vautomute VSetting-VSVR=VVSVR -15% VVSVR* 7 VVSVR *12 VVSVR *13 VVSVR* 48 +15% V VPO- -15% +15% V VPO+ -15% +15% V VU Auto-tristate supply The IC is set in tristate if VSP-VSM voltage VSP is more than this value Relative maximum value Vautomute VSetting-VSVR=VVSVR Auto-tristate supply voltage VSP Absolute maximum value -15% +15% V VUC The IC is set in tristate if VSP-VSM is higher than this value 60 63 66 V 16/64 TDA7572 Table 7. Symbol V14 - UVLO V14Auto-tristate supply voltage V14 negative slope Auto-tristate supply voltage V14 positive slope The IC is kept in tristate if 14V VSM become lower than this value The IC is goes out from tristate if 14V-VSM become higher than this value 5.5 Electrical specifications Under voltage lockout (continued) Parameters Test conditions Min. Typ. Max. Units 7 V V14+ 6.5 8 V V V14h V14su Auto-tristate 14V voltage Comparator hysteresis for autotristate threshold hysteresis Step-up tristate Auto-mute supply voltage V14 negative slope Auto-mute supply voltage V14 positive slope The step-up is in tristate when voltage lower than this threshold The IC goes in mute if 14V-VSM become lower than this value 0.8 5 V14+ 0.7V V14V+ + 40mV 8 V14+ 1.2V V14V+ + 170mV V V14mute- V V14mute+ The IC goes in play if 14V-VSM become higher than this value SVR - UVLO The IC is kept in tristate if VSvr VSM become less than this value Vautomute VSetting-VSVR=VVSVR The IC is goes out from tristate if Vvr - VSM become higher than this value Vautomute VSetting-VSVR=VVSVR Auto-tristate SVR Voltage hysteresis Comparator hysteresis for autotristate threshold Vautomute VSetting-VSVR=VVSVR 0.40 X VVSVR 1.2V X VVSVR V 5 x VVSVR Vsvr- Auto-tristate SVR voltage negative slope -15% +15% V Vsvr+ Auto-tristate SVR voltage positive slope -15% 6 x VVSVR +15% V VPOH 17/64 Electrical specifications TDA7572 4.3.3 Table 8. Symbol Input stage Input stage Parameters Test conditions Min. Typ. Max. Units Input diff. amp./ gain attenuator RIN, No compress ion Input resistance INLEVEL1=0, INLEVEL0=0 RIN max compress ion INLEVEL1=0, INLEVEL0=1 INLEVEL1=1, INLEVEL0=0 INLEVEL1=1, INLEVEL0=1 INLEVEL1=0, INLEVEL0=0 Input clipping level Voltage level of the input that trespassed cause clipping in the preamplifier INLEVEL1=0, INLEVEL0=1 INLEVEL1=1, INLEVEL0=0 INLEVEL1=1, INLEVEL0=1 INLEVEL1=1,INLEVEL0=1 Not tested in production AIN_0 (VAOUT-VSVR) / (VInP-VinM) INLEVEL1=0, INLEVEL0=0, no compression (VAOUT- VSVR) / (VInP-VinM) INLEVEL1=0, INLEVEL0=1, no compression Input stage gain AIN_1 (VAOUT- VSVR) / (VInP-VinM) INLEVEL1=1, INLEVEL0=0 no compression (VAOUT- VSVR) / (VInP-VinM) INLEVEL1=1, INLEVEL0=1, no compression AOUT output voltage swing AOUT output swing With respect to SVR, 10K loading to a buffered version of SVR With respect to SVR, 10K loading to a buffered version of SVR Vin=1Vrms, f=20-20KHz, INLEVEL1=0, INLEVEL0=0, no compression 0.01 -6.3 -5.3 -4.3 dB -30% -30% -30% -30% 2 7 2.6 9.5 -10 +10 15.6 12 16 12 +30% +30% +30% +30% VRMS VRMS VRMS VRMS INLEVEL1=0, INLEVEL0=0 INLEVEL1=0, INLEVEL0=1 INLEVEL1=1, INLEVEL0=0 INLEVEL1=1, INLEVEL0=1 -30% -30% -30% -30% 20 12 22 12 +30% +30% +30% +30% K VInMax -4 -3 -2 dB AIN_2 -15 -14 -13 dB AIN_3 -17.6 -16.6 -15.6 dB VoutH VoutL 2 -2 V V AOUTTHD THD 0.05 % 18/64 TDA7572 Table 8. Symbol Electrical specifications Input stage Parameters Test conditions Vin=1KHz square wave, 2Vpp, INLEVEL1=0, INLEVEL0=0, no compression Time to transition from 10% to 90% Duty cycle of the Clipping signal when there is 5% distortion at the output of AOUT, f=1KHz, RL =10kOhm Vin=1Vrms, INLEVEL1=0, INLEVEL0=0 VCM=1VRMS @1KHz CMRR= AVDIFF/AVCM INLEVEL1=0, INLEVEL0=0 No compressor VCM=1VRMS @1KHz INLEVEL1=0, INLEVEL0=0 No compressor VCM=1VRMS @1KHz INLEVEL1=1, INLEVEL0=0 No compressor VCM=1VRMS @1KHz INLEVEL1=0, INLEVEL0=1 No compressor VCM=1VRMS @1KHz INLEVEL1=1, INLEVEL0=1 No compressor freq<10KHz VOffset with respect to SVR Rin=100 ohms, Mute state Noise at output of this stage f = 20-20KHz, Rinput = 100ohms A weighting TBD 15 25 Min. Typ. Max. Units Output slew rate 8 S % AOUT clip detector f-3dB Frequency response 20 KHz CMRR Common Mode Rejection Ratio 47 dB CG Common gain 51 dB CG Common gain 51 dB CG Common gain 51 dB CG Common gain Power Supply Rejection, Vsp supply Output offset 51 dB PSRR Voffset 60 -4 80 0 +4 dB mV Eno Noise 7 10 VRMS Gain compressor INLEVEL1=0, INLEVEL0=0 INLEVEL1=0, INLEVEL0=1 Maximum attenuation INLEVEL1=1, INLEVEL0=0 INLEVEL1=1, INLEVEL0=1 -25 -34 -23 -32 -21 -30 -21 -30 -19 -28 -17 -26 dB 19/64 Electrical specifications Table 8. Symbol TDA7572 Input stage Parameters Test conditions INLEVEL1=0, INLEVEL0=0 INLEVEL1=0, INLEVEL0=1 Attenuation step size INLEVEL1=1, INLEVEL0=0 INLEVEL1=1, INLEVEL0=1 Gain Change ZC comparator offset (in the diff. - S.E. block) offset Gain Change ZC comparator offset (in the diff. - S.E. block) offset Observed at AOUT pin ZC crossing must be detected within 50mV of the actual zero crossing, Observed at InvOut pin ZC crossing must be detected 0.550.25 0.480.25 0.55 0.48 0.55+ 0.25 0.48+ 0.25 Min. 0.5-0.25 0.440.25 Typ. 0.5 0.44 Max. 0.5+ 0.25 0.44+ 0.25 dB Units -80 80 mV -220 +220 mV Mute Mute attenuation Charge current Discharge current Mute threshold Unmute threshold Mute to unmute transition voltage Vol IC in mute mode, FastMute=1 Iout=0 IC in unmute, Iout=0 FASTMUTE=1 Vmutepin=1.5Volts VDIGITAL0.1 Mute pin voltage = Dgnd Vin=1Vrms Mute Pin Voltage(57) = 1.5V Mute Pin Voltage(57) = 1.5V Maximum voltage where we must be in complete mute 90 -30% -30% 100 100 +30% +30% 1.5 2.5 0.2 0.3 0.42 Digital GND + 0.1 dB A A V V V V Voh Fast mute Resistance V 550 680 Ohm 420 20/64 TDA7572 Electrical specifications 4.3.4 Table 9. Symbol Oscillator Oscillator Parameters Test conditions Min. Typ. Max. Units Internal oscillator PWMCLOCK=[0 1] FPWM_NOM Switching frequency PWMCLOCK=[1 0] PWMCLOCK=[0 0] CLKDC VCLK_High Duty cycle Maximum voltage level Clock output high value Load = 20Kohm and 100pF to buffered SVR Clock output low value Load = 20Kohm and 100pF to buffered SVR Load = 20Kohm and 100pF to SVR 48 VP25-0.1 100K 120 FPWM_NOM *2 FPWM_NOM /2 50 52 VP25 % V 140K KHz VCLK_Low Minimum voltage level VM25-0.1 VM25 V VCLK-P-P Peak-peak voltage -10% -20% -20% 1.4 4.7 100 100 1.6 +10% +20% +20% 1.7 V A A V V Dither cap charge current Dither pin voltage= 2.5V Dither cap discharge current Peak-peak dither voltage swing Dither external clock determination No dither Peak FPWM increase due to dither Voltage at the dither pin at to select external clock function Voltage at the dither pin at which no dither will occur Cdither=100nF VDIG-0.2 VDGND +0.2 +8 -8 VGND+ 1V +10 -10 +12 -12 VDIG1V V % % Peak FPWM decrease due Cdither=100nF to dither Triangular peak value 21/64 Electrical specifications TDA7572 4.3.5 Table 10. Symbol Modulator Modulator Parameters Test conditions Min. Typ. Max. Units Integrator op. amp. Int_Voff Int_ibias Toff Input offset voltage Input bias current Maximum duty cycle Guaranteed by design Vsp =1 4.4 -2.5 +2.5 500 1.1 mV nA s 4.3.6 Table 11. Symbol VOL_LSD VOH_LSD Gate drive and output stage control Gate drive and output stage control Parameters LSG low voltage LSG high voltage Test conditions Isink = 0.5A Isink = 20mA Isource = 0.5A Isource = 20mA Isink = 0.5A Isink = 20mA 7 9.2 VSP-7 VSP9.2 VSP1.75 VSP0.080 HSG low Z drive tdelay LSG low Z drive tdelay HSG HiZ sink current LSG HiZ source current After a commutation After a commutation VHSG=VSP t>5uS VLSG=VSM , t>5uS 2 2 10 10 150 150 s s mA mA Min. Typ. Max. 1.75 0.080 Units V V VOL_HSD HSG low voltage V VOH_HSD HSG high voltage Isource = 0.5A Isource = 20mA V Overcurrent sensing IlimThresh Range of Ilim Trthresh Vilim Vilim Vitrip Anti-shoo through PVGS_ON PVGS_OFF PFET gate voltage that will block NFET enhancement PFET gate voltage that will allow NFET enhancement -2.5 -3.5 V V Engagement of the current limiting VlimitTreshold=1V w.r.t. VM2p5 Start of cycle by cycle current limiting 0.3 Vlim* 3.0 -15% Vlim * 6.0 1.1 Vlim* 5.0 +15% V V V 22/64 TDA7572 Table 11. Symbol NVGS_ON NVGS_OFF Electrical specifications Gate drive and output stage control (continued) Parameters NFET gate voltage that will block PFET enhancement NFET gate voltage that will allow PFET enhancement Test conditions Min. 2.5 3.5 Typ. Max. Units V V 4.3.7 Table 12. Symbol Diagnostics Diagnostics Parameters Test conditions Min. Typ. Max. Units Turn-on diagnostics/ Power up diagnostics -15% ITEST Test current for short/open Ri set = 56ohm -15% 2.45/(3* Riset) 15 +15% +15% mA RISET allowed range VLSSHRT VNOP Short threshold to lower supply rail Normal operation thresholds Short to supply Shorted load Normal load Open load Test charge current tTEST Test time 5.6 -Vs +1 -Vs+2 -Vs+8 6 .025 2 -30% 60 10A 80 +30% 100 1 -Vs+5.5 ohm V V mV V V A ms Permanent Diagnostics VoffACT VoffACT DC offset detected DC offset not detected, normal operation allowed +-3 +-1.2 Volts Volts Temperature TWARN Chip thermal warning Chip thermal warning hysteresis T Chip thermal shutdown Shutdown hysteresis External thermal warning External thermal warning hysteresis 135 3 155 3 -10% Vdig*0.0 30 150 5 160 5 VDIG *.4 165 7 175 7 +10% Vdig*0. 044 C C V V C 23/64 Electrical specifications Table 12. Symbol TDA7572 Diagnostics (continued) Parameters Ext thermal shut down Ext thermal shut down hysteresis Test conditions Min. -15% Vdig*0.0 32 Typ. VDIG *.36 Max. +15% Vdig*0. 046 Units V V Supply Isense Supply sense trip voltage AOUT levels that allow sensing of supply current Duration of AOUT under threshold to allow supply current sensing Issenp IssenM -25% 200 -500 80 16 20 25 3 mV V +25% 700 500 ms A nA 4.4 Table 13. Symbol Voltage booster Voltage booster Parameters Test conditions Min. Typ. Max. Units Current mode control topology BSTDCMAX BSTDCMIN BSTREF Max duty cycle Min duty cycle Vref 0 -8% -100 -0.6 0.4 55 -0.6 0.120 VVsense = Vreference DC=0% 0.220 3 16 0.440 V ms 0.8 2.5 +8% 100 58 1.2 65 58 0.350 88 % % V nA V %D.C. per mV %D.C. V %D.C. per mV IBIASBSTREF Vsense input bias current VSENSE_UL BSTVGain Vsense pin allowed voltage range Voltage-error gain Duty cycle/BSTVSense BSTDCNOM Nominal duty cycle Csense_UL Csense gain Csense pin allowed voltage range Csense gain Duty cycle / Csense VC_SENSE at max current CsenseTrip TSS Ilimit trip point Soft-start step period not yet tested (to be confirmed) Soft start steps 24/64 TDA7572 Table 13. Symbol VOH_BST VOL_BST Electrical specifications Voltage booster Parameters BST gate high voltage BST gate low voltage Test conditions Isource = 0.5A Isource = 20mA Isink = 0.5A Isink = 20mA Min. 7 9.2 1.75V 0.080 Typ. Max. Units V V 4.4.1 Table 14. Symbol Digital to analog converter Digital to analog converter Parameters Dynamic range at -60dBFS Noise floor Test conditions At output of analog filter -60dBFS input 1KHz sine tone At output of analog filter after > 25mS of -97dBFS input 20-20k Hz flat Input=-1.5dBFS The DAC output is limited to prevent operation in regions of degraded DAC performance. This spec represents the performance at this maximum practical value Must engage after 25mS of <96dbFS input signal Magnitude of -1.5dBFS sine, 1 KHz 20 -10% 1.8K 2.1 2.5K Min. 80 Typ. 90 Max. Units dB 20 V THD+N at maximum useful input level -60 dB Silent Mute Differential output voltage Output resistance 30 +10% 2.8K ms Vrms Ohms 25/64 Electrical specifications TDA7572 4.4.2 Table 15. Symbol ISCL/CLIP_L I/O pin characteristics I/O pin characteristics Parameters SCL/CLIP_L pin leakage current VSCL/CLIP_L <375mV Test conditions Min. -15 1 Typ. Max. 15 Units A mA ISCL/CLIP_L SCL/CLIP_L pin sink VOH, digital output pins VOL digital output pins VINL VINH ADDR0 ADDR1 threshold low ADDR0 ADDR1 threshold high 1.5 2.3 1 4 V V 4.4.3 Table 16. Symbol Int_OLGain PSRR Int_Voff Int_ibias Op. amp. cells Op. amp. cells Parameters Open loop voltage gain VSP power supply rejection Input offset voltage Input bias current Test conditions Guaranteed by design PSRR = 20*log10(Vsp/= F < 10KHz VSP ripple=1Vrms Guaranteed by design Guaranteed by design Guaranteed by design Min. 80 -50 -3 3 500 Typ. Max. Units dB dB mV nA 4.4.4 Table 17. Symbol Isource Isink Shunt Shunt Parameters Source current Sink current Shunt drive current activation Vs. Mute pin voltage (the shunt current is sourced when Vmute is lower than the threshold). Shunt drive current activation hysteresis Test conditions Min. 70 70 Typ. 100 100 Max. 130 130 Units A A Vsd 0.8 1.2 V Vsdh 80 140 mV 26/64 TDA7572 Electrical specifications 4.4.5 Application information These are required parameters of the overall operation of the Cortina IC in its application circuit and will form the overall functional testing for Cortina Table 18. Symbol Analog operating characteristics Parameters Test conditions 1W, 100Hz, VSP=14.4 Rl=2 ohm Only modulator (1) Min. Typ. Max. Units 0.5 % THD+Noise 4W VCC = 14V and VCC = 42V FR =1 00Hz (1) 0.3 0.4 400 -100 -200 -70 0 0 0 100 200 70 % % Vrms mV mV 50W FR=1kHz VCC = 42V Output noise Output offset Output offset VSP=14.4V (1) VCC = 14.4V VCC = 42V Offset modulator only (VCC =14.4V) 1. Note: the measure is affected by the testing board noise. 27/64 I2C and mode control TDA7572 5 I2C and mode control The Mode1 and Mode0 pins are used to enable TDA7572. These perform the function of bringing the IC out of standby (typically handled by a single standby pin on most audio IC's) as well as determining if the I2C bus is active or if power-up Diagnostics shall automatically occurs. The Auto-mute Voltage pin is used to provide an under-voltage-lockout for the IC. Using a resistor divider between V2P5 and SVR a series of comparator prevent the IC from powerup further until sufficient voltage is present at VSP and SVR(equal to GND in the split supply case. Once this voltage requirement is met, the chip is forced into mute (a special, direct form of mute that does not use or act upon the MUTE pin) under a second, higher voltage threshold is met. At this point the IC performs its normal power-up, controlled by the state of the MODE pins and the various configuration pins. Refer to the under-voltage lockout (UVLO) section of the documentation for details on these thresholds. The Auto-mute Voltage pin is also used to provide an over-voltage shutdown based on absolute voltage of VSP-VSM. Table 19. Mode1 0 Power-up mode control Mode0 0 Standby, or "Off" NO I2C BUS mode TDA7572 enabled Configuration defaults read from pin I2C disabled Power-Up-Diagnostics disabled I2C BUS mode TDA7572 enabled I2C enabled Power-Up-Diagnostics disabled TDA7572 enabled Configuration defaults read from pins I2C disabled Power-Up-Diagnostics enabled DIAGNOSTIC mode TDA7572 enabled Configuration defaults read from pins I2C disabled Power-Up-Diagnostics enabled State/function 0 1 1 1 1 0 When I2C bus is active, determined by the Mode0 and Mode1 pins, any operating mode of the IC may be modified and diagnostics may be controlled and results read back. 28/64 TDA7572 The protocol used for the bus is the following and comprises: I2C and mode control a start condition (S) a chip address byte (the LSB bit determines read / write transmission) a subaddress byte a sequence of data (N-bytes + acknowledge) a stop condition (P) Table 20. Addresses Chip address Subaddress Data [7:0] MSB S A LSB A A A A A A R/W ACK S = Start MSB X XIAAAA LSB A ACK MSB DATA LSB ACK P R/W = "0" -> Receive-Mode (Chip could be programmed by P) "1" -> Transmission-Mode (Data could be received by P) I = Auto increment - when 1, the address is automatically increased for each byte transferred X: not used ACK = Acknowledge P = Stop MAX CLOCK SPEED 500kbits/s The I2C address is user determined by pins ADDR1 and ADDR0. See table below: Table 21. MSB A6 0 A5 1 A4 0 A3 0 A2 0 A1 ADDR1 A0 ADDR0 I2C chip address LSB R/W X Write procedure: Two possible write procedures are possible: 1. 2. without increment: the I bit is set to 0 and the register is addressed by the subaddress. Only this register is written by the data following the subaddress byte. with increment: the I bit is set to 1 and the first register read is the one addressed by subaddress. Are written the register from this address up to stop bit or the reaching of last register. Example of write instruction with increment: Device Address S 0011000 Register Address A ADDR A MS1 R/W 0 DATA 1 A LS1 A MS2 DATA 2 A LS2 A MSn DATA n A LSn A P 29/64 I2C and mode control TDA7572 Read Procedure: Two possible read procedures are possible: 1. without increment: the I bit is set to 0 and the register is addressed by the subaddress sent in the previous write procedure. Only this register is written by the data following the address. with increment: the I bit is set to 1 and the first register read is the one addressed by subaddress sent in the previous write procedure. Are written the register from this address up to stop bit or the reaching of last register. 2. Example of read instruction with increment and previous addressing by write instruction and restart bit (Sr) Device R/W Address S 0011000 0 A Register Address ADDR Device R/W Address A Sr 0011000 1 DATA 1 DATA 2 DATA n A MS1 A LS1 A MS2 A LS2 A MSn A LSn NA P In the following tables are reported the meaning of each I2C bus present in the device. 30/64 TDA7572 I2C and mode control 5.1 Table 22. MSB D7 R/W 1 Input control register Subaddress: XXI00001. Input control register LSB D6 R/W 1 D5 R/W 1 D4 R/W 1 D3 R/W 0 D2 R/W 0 D1 R/W 0 Read from PLL/Gain pin D0 R/W 1 Power-up default, I2C enabled Power-up default I2C disabled Function AttackSel (pin)=1 [11] AttackSel (pin)=0 [10] AttackSel (pin)=1 [11] AttackSel (pin)=0 [10] CompEnable (pin)=1 [01] CompEnable (pin)=0 [00] 0 Mute 1 0 Mute Play INLEVEL0 Low Gain High Gain Gain table Compressor disabled THD=0.02; Nb. step=1 THD=3.0; Nb. step=2 THD=0.02; Nb. step=1 THD=3.0; Nb. step=2 THD=5.0; Nb. step=3 Not used Release (400kHz clock) 20.48ms 40.96ms 81.92ms 163.4ms Attack (400kHz clock) 160s 320s 640s 1.28ms 0 1 0 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 31/64 I2C and mode control TDA7572 5.2 Table 23. MSB D7 R/W1TC Faults 1 register Subaddress: XXI 00010. Faults 1 register LSB D6 R/W1TC D5 R/W1TC D4 R/W 0 D3 R/W1TC 0 D2 R/W1TC 0 D1 R/W1TC 0 D0 R/W1TC 0 Power-up default GNDshort 0 1 Short to ground detected VCCshort 0 1 Short to a "Vcc" detected Open/offset 0 1 Open load detected during LOADshort 0 1 Short across the load detected DiagnENB Diagnostic disabled or finished To run the Diagnostic/diagnostic in progress UVLO flag UVLO event NOT USED NOT USED Function 0 1 32/64 TDA7572 I2C and mode control 5.3 Table 24. MSB D7 Faults 2 register Subaddress: XXI 00011. Faults 2 register LSB D6 D5 R/W1TC 0 D4 R/W1TC 0 D3 R/W1TC 0 D2 R/W1TC 0 D1 R/W1TC 0 D0 R/W1TC 0 Power-up default Clip 0 1 Clipping of modulator and/or preamplifier Offset 0 1 Offset detected IsenTrip 0 1 Power supply current threshold trespass IoutTrip 0 1 Output stage current limiting has been enabled ExtTwarn 0 1 External thermal warning threshold trespassed TJwarn 0 1 Internal thermal warning threshold trespassed NOT USED NOT USED Function 33/64 I2C and mode control TDA7572 5.4 Table 25. MSB D7 R/W 0 0 Control register Subaddress: XXI 00100. Control register LSB D6 R/W 0 0 D5 R/W 0 0 D4 R/W 0 0 D3 R/W 1 1 D2 R/W 0 SDA/SCR_ENB D1 R/W 1 1 D0 R/W 0 0 Power-up default I2C enabled Power-up Default I2C disabled Mute speed Slow Mute Fast Mute OffsetENB 0 1 Enable the offset detection PassFET Control ENB Enable the SCR intervention BOOST 0 1 Enable the step-up L/R Read left channel from I2S Read right channel from I2S Fratio1 Fs = 96 kHz Fs= 192 kHz Fratio0 Bass range digital input Fs= 38 to 48 kHz Full band digital input (Fs=96 or 192 kHz selectable by Fratio1) DACEnb Function 0 1 0 1 0 1 0 1 0 1 0 1 Enable DAC operation 34/64 TDA7572 I2C and mode control 5.5 Table 26. MSB D7 R/W 0 0 D6 Modulator register Subaddress: XXI 00101. Modulator register LSB D5 R/W 1 0 D4 R/W 0 0 D3 R/W 0 0 D2 R/W 1 SCL/InLevel1 pin D1 R/W D0 R/W 0 1 Power-up default I2C disabled Power-up default I2C enabled SHUNT Turn-on shunt NOT USED INLEVEL1 0 1 0 1 0 1 0 1 High level couple DAC synchronization Synchronize the modulator with the DAC SVR Turn On the charge of SVR Tristate Tristate modulator PWMClock 55kHz 110kHz 220kHz 110kHz Function R/W 1 1 0 1 0 0 1 1 0 1 0 1 35/64 I2C and mode control TDA7572 5.6 Table 27. MSB D7 R/W Testing register Subaddress: XXI 00110. Testing register LSB D6 R/W D5 R/W D4 R/W D3 R/W 0 D2 R/W 0 D1 R/W 0 D0 R/W 0 Power-up default Or ZC 0 1 (nIN xnor pIN) or (nOUT xnor pOUT) are put on the clipping output Ramp 0 1 Generate a ramp on the compressor gain TestDriving 0 1 Turn off limitation of driving current for the external MOS Fast 0 1 All time constant used in the logic block are devided by 100 Not used Not used Function 36/64 TDA7572 Input stage and gain compressor 6 6.1 Input stage and gain compressor Input stage The input stage accepts differential analog audio and provides a single ended output that is referenced to SVR, a slowly changing reference signal that is close to VCC/2. This signal is present on the pin 6 (SVR). Four input stage gains are selectable, chosen such that input signal levels of either 2VRMS, 2.6VRMS, 7VRMS, or 9.7VRMS will provide full scale unclipped output swing of this stage. The variable gain is realized by a single ended input attenuator (with respect to SVR), such that both differential and common-mode voltages are attenuated, and by, mean of a reconfiguration of the Op-Amp feedback. These are controlled by two bits, one controlling the input attenuator, and the other controlling the Op-Amp configuration. The bits INLEVEL0 in the InputControl register (register addr 1, bit 1) and INLEVEL1 in the Modulator register (register addr. 5, bit 2) determine the gain selection. The default value of INLEVEL0 and INLEVEL1 bits are determined by the voltage levels at power-up on pins PLL/INLEVEL0 (pin 63) pin and SCL/INLEVEL1 (pin 62) respectively allowing gain selection without the requirement of an I2C bus. INLEVEL0 controls the input attenuator, and INLEVEL1 controls the configuration of the feedback around the op. amp. INP - pin 12 INM - pin 13 AOUT - pin 14 SCL/INLEVEL1 - pin62 PLL/INLEVEL0 - pin63 : positive input : negative input : output : gain selection bit 1 : gain selection bit 0 This stage is powered from 2.5Volts, centered around SVR. Output swing is nominally 2 volts. The input common mode range is a function of the gain setting, the electrical parameters section must be consulted for details. It is expected that the inputs will be ac coupled, and because of this consideration must be given to the rate of change of SVR, as rapid changes to SVR could cause the inputs of this amplifier to run out of common mode range. i.e. the input decoupling capacitors can not charge fast enough to keep up with SVR 6.2 Gain compressor A gain compressor is integrated in the front end of this stage, which provides up to 16dB of differential attenuation in approximately 0.5dB steps, varying somewhat depending on gain configuration. Compressor aggressiveness is programmable by the I2C data/AttackSel pin (providing a choice from two attack-time/decay-time pairs) in non-I2C bus mode, or by I2C bus with 2 bits each for attack and decay and 2 bits for the distortion-to-attenuation table. These are bits ATTACK[1:0], DECAY[1:0], and TABLE[1:0] in the InputControl register. The ADDR1/CompEnable pin is used in non-I2C mode to enable or disable gain compression entirely. The gain compressor operates by monitoring the estimated in THD due to clipping, overmodulation or over-current and commanding a change in the input attenuation based on the THD estimate. The input attenuator has 32 discrete steps. THD is estimated by measuring the time period between zero crossings where there is no clipping and the time when there 37/64 Input stage and gain compressor TDA7572 is clipping during that period. The THD estimate is calculated from the ratio between these times. Clipping means are any of the following conditions occurred: maximum modulation reached, output current limiting active, or voltage clipping at the AOUT pin. These are used to estimate THD, which is then mapped to a desired number of discrete steps of gain reduction. Attenuation is then changed at the next zero crossing of the signal at the Input Stage block The attack time sets the minimum time allowed between gain reductions. At low frequency signals, where the time between zero crossings is greater than the attack time, the attack rate is dictated by the signal frequency, rather than this setting. Similarly, the decay time sets the minimum time allowed between gain increases, with the same caveats about rate dictated by the signal frequency. The major tuning control here is the distortion-to-attenuation lookup table. It will determine how aggressively to operate and thus the relative amount of audible artifact. Decay time adjustment can be varied for audible effect and to mange average power. Following are reported the correspondence between I2C bus registers and coefficients for Attack and decay time. The first table reports the one for compressor setting: 6.2.1 Setting in I2C bus mode GainTable[1:0]: Selects the distortion versus gain step size table to be used, including the ability to disable the gain compressor. Table 28. Distortion versus gain step size Pseudo THD,% / T2/T1 ratio Number of gain steps GainTable [1:0] 00 01 Gain compressor disabled 0.02 3.0 0.02 3.0 5.0 0.02 3.0 5.0 15.0 1 2 1 2 3 1 2 3 4 10 11 RELEASE[1:0]: Sets the maximum release rate of the gain compressor according to the table below: Table 29. Sets the maximum release rate of the gain compressor Clock counts 213 214 2 2 15 16 Release [1:0] 00 01 10 11 Nominal time at 400KHz clock 20.48ms 40.96ms 81.92ms 163.4ms 38/64 TDA7572 Input stage and gain compressor ATTACK[1:0]: Sets the maximum Attack rate of the gain compressor according to the table below: Table 30. Sets the maximum attack rate of the gain compressor Clock counts 2 6 Attack [1:0] 00 01 10 11 Nominal time at 400KHz clock 160s 320s 640s 1.28ms 27 2 2 8 9 Setting in NOI2CBUS mode: I2CDATA/AttackSel - pin 51 -> Attack/release rate selection ADDR1/CompEnable - pin 54 -> Gain compression effort selection Table 31. Attack/release rate and gain compression effort selection DGND Attack[1:0] = "10" Release[1:0] = "10" GainTable[1:0]="00" VDIG Attack[1:0] = "11" Release[1:0] = "11" GainTable[1:0]="01" INPUT PIN/VALUE Pin 51 Pin 54 6.2.2 Soft-mute function, without pre-limiter Well-behaved over-modulation protection and current-limiting allow this IC to not require a pre-limiter before the modulator. This allows the amplifier to always take advantage of the available supply voltage. A limited output voltage can be done in a crude manner by using AOUT's max output swing, and counting on its clipping signal to drive the compressor. A soft mute/unmute is incorporated at AOUT. It works by slowly muxing AOUT from the input signal to SVR. In this way, dc offsets occurring in any upstream stages are kept inaudible. The mux slew time is determined by the voltage slew rate at the MUTE_L pin (pin 10), which is asserted low. Mute can by driven either be by external means, or controlled by I2C command. The MUTE bit, present in the input control register (D0, InputControl register), controls muting by discharging or charging the MUTE_L pin. The default value for this bit for NOI2C mode is 0 that lead to a charging of mute cap. Abrupt muting is available by use of the MuteSpeed bit. When MuteSpeed is asserted, MUTE_L is rapidly charged and discharged by a small resistance (approximately 500 ohms). In the pictures below are reported the two application circuits and the internal circuitry of mute correspondent to. Figure 3. Mute by external command 100A External Mute Mute_L AC00015 39/64 Input stage and gain compressor Figure 4. Mute by I2C bus command TDA7572 100A Mute_L 500Ohm 200A Mute and not(MuteSpeed) Mute and MuteSpeed AC00016 Note: when the modulator is set in TRISTATE the mute pin is fast-discharged by the fast-mute internal circuitry. When the modulator is take back out of TRISTATE the preamplifier is put in play back by a fast un-mute transient. 40/64 TDA7572 Modulator 7 Modulator The modulator PWM is the main function of device. Two modulators are provided which are operated independently but configured for bridged mono operations. They are synchronized by virtue of the common clock that drives them and operate as a three-state modulator (phase shifting PWM modulation type) when the audio is inverted going to one modulator. This inversion is accommodated by a dedicated inverter block present between the InvIn and InvOut pin. Figure 5. Modulator block diagram RQ R2 MOD0 HB1Out Diff -To S.E. MOD1 VHB1OutF R1 Aout InvOut Inv SVR InvIn MOD2 VHB2OutF OSC OSCOut MOD1 R1 RQ R2 HB2Out AC00017 The above scheme reports the application circuits and internal block involved in the PWM modulator. The analog signal is differential to single ended converted by the amplifier. The signal obtained is inserted as current in the virtual ground of modulator MOD0. The conversion is obtained trough R1 resistor. The same signal, output of AOUT, is inverted and inserted in the virtual ground MOD1 through the resistor R1. In order to obtain a PWM signal a square wave is inserted in both MOD0 and MOD1 through the RQ resistor. The Gain of Modulator is equal to the ratio of R1/R2. In Order to choose the value of RQ has to take into account the stability of modulator, guarantee if the following relation is respected: VP2.5 VAOUTmax VSP - VSVR Equation 1 ---------------- > --------------------------------- + ----------------------------------RQ R1 R2 Clocked PWM modulators using an integrated T-network double integrator are implemented. The end user has the ability to trade distortion for EMI by switching faster or slower, controlled by PWMClock[1:0] in the modulator register. 41/64 Modulator Table 32. PWMClock table Ratio FNOM/2 FNOM FNOM*2 FNOM Nominal frequency 55KHz 110KHz 220KHz 110KHz TDA7572 PWMClock [1:0] 00 01 10 11 Pulse injection is being used with the clocked PWM scheme to prevent missing pulses from an over-modulation condition. The minimum pulse width is dynamically determined by looking at the delay from the comparator output to the actual switching of the FET stage. This delay is used to extend any pulses from the modulator that would otherwise be too short. Circuitry is provided to keep the integrator hovering near the level at which limiting first occurred, which prevents transients once we leave the over modulation condition. This is done by summing in a current that is proportional to the amount of time that the pulse is extended. Since only three- state modulation is supported, it may prove necessary to slightly delay the clock going to one modulator to prevent the noise from the switching of one modulator affecting the second modulator when there is no audio input. This can be done with a small RC on the clock feeding one modulator. The same result could be obtained adding the RC on the feedback feeding one modulator. The reference voltage of the modulator changes from SVR at it's input, to Vcc/2 at its output. This allows output signal to be centered between the supply rails, increasing unclipped output voltage swing by preventing asymmetric clipping. This is accomplished using the LVLSFT pin, as described in the previous paragraph. It has been pointed out that there is potential for abrupt transients at the output stage, as this scheme will attempt to have the outputs track VCC/2, while it may be better for avoiding pops to have them rise slowly with SVR. The end user needs to make this decision by making or not the connection between HVCC and LVLSFT pin. Will not be present pop noise in a system with perfect symmetry between the two modulators branch. Pop noise will rise with increasing of asymmetry. 7.1 FET drive Gate drive circuits are provided to drive complementary external FETS. An internal regulator to supply the low side gate drivers provides a voltage 10V above VSM. This fully enhances the FETs without exceeding their VGS limits. A separate regulator 10V below VSP, is used for the high side gate drivers. Shoot-through is prevented by sensing VGS of each FET with a dedicated sense line (GateSensing), and blocking the opposite FET turn-on if the active FET in a 1/2 bridge has a |VGS|> |VThreshold|. This allows discrete components to be used to adjust gate charging without concern over shoot-through. The drivers are capable to provide high current for a short time (about 5s) and a lower current after this time(~150mA). This is done to give enough charge current at the commutation and avoid short-cut overcurrent. The VDS of the enhanced FET of each 1/2 bridge is used monitor current and detect overcurrent condition. The sensed VDS signal is blanked such that sensing is only active when the FET is enhanced and any turn on transients have settled. There are two type of overcurrent intervention: current limitation, cycle-by-cycle limitation. The current limitation 42/64 TDA7572 Modulator consists in a clipping of current when the first threshold for VDS is trespassed. It is obtained by sink or source current to the virtual ground of modulator integrator. The cycle-by-cycle limitation is a strong limitation. If the second VDS threshold is trespassed for more than about 2s the half bridge is tri-stated. If this condition persists for more then four PWM periods the modulator is definitely tri-stated. It is possible setting the threshold VDS voltage for the current limiting by the pin IlimitThreshold: the first threshold is the value voltage value of this pin (referred to VN2.5), the second one is the same value multiply by the factor 1.5. 7.2 ANTI-POP shunt driver The device is provided by a driver able to control an anti-pop shunt MOS which is connectable in series or in parallel to the load. During the mute-to-play or play-to-mute transition an external MOS is able to disconnect (MOS in series) or short (MOS in parallel) the speaker in order to reduce the audible pop noise. The shunt driver is able to source or sink a predefined current (see Table 17). The following diagram reports the temporal behave of current at the shunt pin respect to the voltage on the mute pin in NOI2CBUS mode. Figure 6. Current sourced by the shunt pin in NO I2Cbus mode Vmute Vsd+Vsdh Isource AC00018 In I2Cbus mode it is possible to change the driver current direction only by change the bit D0 of byte 5. When the bit is set to 1 the current is sourced. By default the current is sourced. 43/64 DAC TDA7572 8 DAC A one channel DAC is provided. A balance between die area and functionality has been made - the interpolator function required for full bandwidth operation has been off-loaded to an external DSP. This allows Bass-only operation of the DAC without any processing assistance, while full bandwidth audio requires external interpolation assistance. The DAC has a differential output: positive output DAC1(32) negative output DAC2(31) On these pins are present a four level squared wave, composed by the differences of two PWM wave have one an amplitude 16 times lower than the other. The output voltage on DAC1 and DAC2 is compatible to the digital supply VDIG. Figure 7. DAC circuit diagram CF R=20k RF INP CF RF=4.7k DAC2 INM R=2.5k SVR/DGND AC00019 where is filtered by means of capacitors and put in the AOUT Differential to single-ended input, as reported in the picture above. The maximum signal present output of converter is 1.4 Vrms. The setting to use for the Diff-to-SE converter is Gain= -3dB (INLEVEL1=0,INLEVEL0=0). Communication is through a standard I2S port. I2C is available too. Acting on the I2C Control registers it is possible turn-on the DAC (DACEnb) and choose the configuration (Fratio(1:0)). With Fratio = "00"/"01" the configuration is for bass only. The Input sample frequency is 48kHz (Fs). In case of Fratio = "10" the configuration is for full band. The input sample rate for this case is 96kHz (Fs) and the first x2 interpolator has to be implemented off-line in the DSP. A well checked structure to realize could be the following: Oversampling Filter Type Taps, bit Attenuation Increasing word rate from Fs to 2Fs. Remez filter, half band 57, 12 50db attenuation out of 0.55Fs Coefficients It is an Half-Band filter then we have only 15 coefficients (see following) Coefficients: -11,11,-16,22,-30,40,-53,69,-91,122,-168,247,-426,1300,2047,1300,.... 44/64 TDA7572 DAC In case of Fratio = "11" the configuration is still for full band. The input sample rate for this case is 192kHz (Fs) and the first x4 interpolator has to be implemented off-line in the DSP. For the first x2 interpolator could be used the precedent, for the second one should be used the following: Oversampling Filter Type Taps, bit Increasing word rate from 2Fs to 4Fs. Remez filter, half band 7, 12 Attenuation 50db attenuation out of 0.77*(2Fs) Coefficients It is an Half-Band filter then we have only 3 coefficients (see following) Coefficients: -190, 1199,2047,... To implement the first interpolator are necessary 28 memory access, 14 sum and14 MAC (multiply with accumulation) at rate Fs. For the second one are, instead, enough 4 memory access, 2 sum and 2 MAC at rate 2Fs. In the following schematic is reported the structure for the two interpolator eventually to implement in the DSP. Figure 8. Two interpolator structure diagram 18 bit 19 bit 30 bit 34 bit RAM 32x18bit 12 bit 18 bit ROM 16x12bit REG AC00020 The I2S format is used to transfer audio samples: Figure 9. I2S format diagram WS SCL SDA MSB LSB MSB LSB MSB AC00021 LEFT RIGHT Where the WS is a clock at frequency Fs(48,96,192kHz) and discern which channel is transferred, where the SCL is the interface clock at 64*Fs(3.07, 6.14, 12.29MHz). The SDA are the bit transferred, 32 for each channel. Only the first 18 bits are taken into account and only one channel. The Control register bit L/R selects the channel amplified. The internal clock used to clock the DAC logic is obtained from the PLL that lock to the I2S clock present on pin SCL. In order to work the PLL needs a RC series network connected to pin PLL/INLEVEL0 (pin 44). Optimal value are C=100nF, R=33Ohm with in parallel an 1.8pF capacitance 45/64 Step-up TDA7572 9 Step-up A current boost controller is provided to allow high power operation in the 14V automotive environment. This is a clocked PWM, current mode control block that drives an external NFET. Following is present the application circuits. Figure 10. Step-up application diagram 14V VSP V14Sense +14V Coil CSense Step-Up Regulator BSTGate R1 BSTSource R2 BSTVSense VSM VSM AC00022 In the Step-up implemented is present a current control loop and a voltage one to fix the output voltage. On the pin BSTVSense is reported the voltage VSP except for the gain of Step-up, here imposed by the ratio R1 and R2. To improve stability, response time and inductor requirements, an inner current control loop has been implemented. The inductor parasitic resistance will be an adequate current sensor, and it is expected that with an RC could be cancelled the zero of the boost inductor. Instead of use the parasitic resistor of inductor a series sensing resistor could be used. The current sensing is take out by the pins V14Sense and Csense. To avoid destructive startup currents, soft startup is provided which functions by increasing the allowed current limit using 4 steps roughly 4ms apart. An overcurrent condition is declared if there is an extended period of high current. Excessive current is detected (by monitoring the voltage across Csense and V14Sense pins) for a period exceeding 20ms, which are considered to be caused by a fault condition, are detected as Csense exceeding a voltage threshold and are handled by forcing a restart of the soft start sequence when over-current is declared. Following are reported the threshold of current limiting. 46/64 TDA7572 Figure 11. Threshold of current limiting diagram VV14Sense - VCSense Step-up Vlimhmax, Vlimlmax 440mV Vlimhmin 260mV Vlimlmin 120mV AC00023 37V 42V Vo The I2C bus register that is set for default to "habilitation" enables the step up. In case of 14V operation or split supply the step-up and no i2c bus mode the step-up is disabled by connects the BSTVSense pin to a reference of at least five volts over VSM. During the testing phase the digital test mode is entered by put Csense pin at least 3V under 14V pin. 47/64 Diagnostics TDA7572 10 Diagnostics Diagnostics are grouped into two categories, those performed only during standby, and those available during amplifier operation. When Mode[1:0] indicate the I2C is active, the RunDiag bit must be set (by an I2C write to the Faults1 register) to initiate diagnostics. When Mode[1:0]indicate the I2C is not active, the state of Mode[1:0] are further decoded to determine if the diagnostics should be run automatically during power-up Diagnostics performed during power-up (Power Up Diagnostic or PUD, sometimes called "Turn-on-diagnostics") are: 1. 2. 3. 4. 1. 2. 3. 4. 5. 6. Output shorted to ground Output shorted to Vs Shorted transducer Open Transducer DC offset across the speaker Die temperature External temperature Output Clipping Output overcurrent Power supply overcurrent During operation the following conditions are continuously monitored: Faults are reported in a simple manner for bus free operation. The open drain WS/Clip_L pin asserts when clipping occurs, and the Address0/Fault_L pin asserts if any there are any other faults. In case of busfree operation the Address0/Fault is the logical OR of all fault conditions. When I2C bus is present, one can read detailed fault status, as well as control the diagnostics being performed via TDA7572's registers, Address0/Fault_L is used to determine which one has to be the I2C bus Address0 of this IC or, in case of DAC operation, it is used to assert when clipping occurs. In this case the Address0 of I2C bus address is automatically set to zero, which implies that only two TDA7572 can be addressed. In any Mode case a clipping output is present. The detailed procedure implemented to manage these faults follows: 10.1 10.1.1 Faults during operation: DC offset across the speaker I2Cbus: If the module of VHOUTF1 - VHOUTF2 > 3Vfor more then 100ms the Offset bit in register Faults2 is set and the external FET's are tristated. The bit is cleared using the W1TC procedure. Resetting the bit removes the tristate mode and modulator operation is restored No I2Cbus: Operation is as above except the fault is also reported by asserting the Address0/Fault_L pin. In order to restart the system is necessary to pass through standby mode. 48/64 TDA7572 Diagnostics 10.1.2 Die temperature I2Cbus: The Twarn bit in register Faults2 bus register is set when the first threshold is exceeded. If the second threshold is exceeded the SCR is enabled (only if the PassFETctrl bit is set to one) which allows the external power switch to latch off, and can only be restarted by removing and reapplying power. Twarn is cleared using the W1TC procedure. No I2Cbus: Operates as above, except the non-latched version (real-time version) of the Twarn bit is reported on the Address0/Fault_L pin. The value of PassFETctrl is determined by the SDA/SCR_Enb pin, which is read at powerup. 10.1.3 External temperature I2C bus: The ExtTwarn bit is set if the voltage at the NTC pin exceeds the first threshold. If the second threshold is exceeded the SCR is enabled (only if the PassFETctrl register is set to one). ExtTwarn is cleared by the W1TC procedure No I2C bus: Operates as above, except the non-latched version (real-time version) of ExtTwarn register is reported on the Address0/Fault pin. The value of PassFETctrl bit is determined by the SDA/SCR_Enb pin, which is read at powerup 10.1.4 Output clipping I2C bus: The Clip bit in the Faults2 register is set when the clipping detected. The Clip bit is cleared by the W1TC procedure. Clipping is detected if there is maximum modulation or over current control at the modulator, or if the AOUT pin clips. No I2C bus: The instantaneous value of clipping, as defined above, is reported on the SCL/CLIP_L pin. The pin is pulled low during a clipping event (assertion level low). DAC Enabled: To handle the case when the DAC is in use and to meet the requirement of a physical clipping signal, the clipping signal is brought out to the Addr0/Fault pin 10.1.5 Output over-current I2C bus: The output current is clipped/limited by pulse injection into the modulator when the qualified VDS of the active FET exceeds the first threshold, at the same time the IoutTrip bit is set. If the second threshold is exceeded the current is cycle-by-cycle limited by switching the FET's off after few microsecond. If the cycle-to-cycle limitation is present for more then 4 cycle the SCR is enabled (only if the PassFETctrl register is set to one) and the external FET are tristated. In case of the SCR is disabled the external FET are not tristated and the limitation still going. The register is cleared by the W1TC procedure. No I2Cbus: In addition to the above, the clipping out pin is engaged by the current limitation. The value of PassFETctrl bit is determined by the SDA/SCR_Enb pin, which is read at powerup 49/64 Diagnostics TDA7572 10.1.6 Power supply overcurrent I2Cbus: The bit IsenTrip is set when the voltage between the ISSENP and ISSENM pins exceeds the threshold. Also, the power control SCR is turned on (only if the PassFETctrl register is set to one). IsenTrip is cleared by the W1TC procedure. No I2Cbus: In addition the above, the non-latched version of IsenTrip register is reported on the Address0/Fault_L pin. The value of PassFETctrl bit is determined by the SDA/SCR_Enb pin, which is read at powerup: NOTE: The Output current is monitored only when the output signal is in the +/-1.2V (see offset detector specification) range for more then 100ms. When this condition is reached a switch present between ISSENM and ISSENP is switched off. Normally this switch shorts the ISSENM pin to the ISSENP, allowing external filter caps to used to condition the current sense signal. 10.1.7 Fault handling Table 33. Fault Fault handling 1st Threshold (Bus mode: I2C/No I2C) - Latch the offset bit - Tristate the modulator 2nd Threshold DC offset - Latch the offset bit and Fault pin - Tristate the modulator - Latch the Twarn bit Die temperature - Latch the Twarn bit - Assert the fault pin - Latch the Clip bit - Assert the SCL_CLIP_L (if no DAC) - Assert the Address0 (if DAC) - Latch the Clip bit - Assert SCL_CLIP_L - Latch the IsenTrip bit - Clip the output current by modulator injection Output overcurrent - Latch the IsenTrip bit - Clip the output current by modulator injection - Latch the IoutTrip bit - The SCR is activated if enabled Power supply overcurrent - Latch the IoutTrip bit - Assert the Fault pin - The SCR is activated if enabled Cycle-to-cycle Current limiting is activated. If the cycle-by-cycle limitation is present for more then four PWM cycles the SCR is activated if the SCR is enabled and the output FET are tristated. If the SCR is disabled the cycle-by cycle limitation keep going. The SCR is activated if enabled Output clipping Note: in legacy mode (no I2C bus) the Output over-current warning information is not reported on the fault pin, while is present on the clipping detector output pin. 50/64 TDA7572 Events that put in tri-state the Modulator: - - - - - - - - - - - Diagnostic on Offset detection Output over-current second threshold trespassed Diagnostic Fault Junction thermal warning External thermal warning Supply current over-threshold Offset detection Over-temperature protection Output over-current second threshold trespassed Supply current over-threshold Diagnostics Events that enable the Fault Pin without I2C bus: Events that enable the SCR: 10.1.8 Faults during power-up: This is a power-up diagnostic useful to detect: load short to ground, load short to supply, short across the transducer, open transducer. The PUD could be performed with and without I2C bus. I2Cbus: setting the bit 4 of Fault1 register the diagnostic begin. The capacitor TestC is then charged by a Thevenin circuits with R = 155 kOhm and supply equal to 1.75V. The value of capacitor is choose in order to have an audible charge ramp and at the same time in order to have an acceptable charge time. The diagnostic time start when the TestC pin reaches the 98% of full charge. During the diagnostic time of 100 ms a current equal to 2.45 I = ----------------------3 RISet The drop across the load produced by this current is continuously monitored. A fault is detected if the drop and/or the absolute value of pin HB1Out and HB2Out are abnormal for the full 100 ms period set when a fault is detected the correspondent bit in the Fault1 register is set and the diagnostic keep running until the fault is present. In case no fault is detected after the 100 ms period the capacitor is discharged and the current on the load is reduced down to zero. When this current is at the 2% of is nominal value the bit 4 of Fault1 register is set to zero. Pulling this register the operator could understand the state of diagnostic. Note that during diagnostic cycle the output FET are in tristate. No I2C bus: The operation of diagnostic is equal to the one with I2C bus. The only differences are about the habilitation, which is selected by the mode, and the assertion of fault presence, which is done trough the addr0/Fault pin. At the end of diagnostic the Fault pin is for sure low and the external FET start to commute. These are the thresholds to take into account for short to ground and short to supply Normal operation VSM+2V VSM+5.5V SGND Voltage threshold VSM VSM+1V X X VSM+8V SVCC VSP 51/64 Diagnostics TDA7572 These are instead the thresholds to take into account for the short and open transducers with some example with a predefined current SL Voltage threshold Itest=14mA Itest=140mA 6 mV 0.4 0.04 X Normal load 20 mV 1.43 0.14 1 71 7.1 X 2 143 14.3 OL - 52/64 TDA7572 Oscillator 11 Oscillator A common clock is needed to run all switching blocks at one frequency to avoid beating. The internally generated clock is used for the PWM modulators and to run the dc-dc converter. To blur the EMI spectrum, sub-audible frequency dither incorporated. When the DITH-sel pin is logic gnd then the internal oscillator operates without dither. With a cap there is +-100UA dithering functions Putting DITH-sel to VDIG allows an external clock to be accepted from CLKin-out at 4X the selected frequency Clock out is referred to VP2.5 and VM2.5, while external clock input is referred to DGND and VDIG External CLKin-out is always active. When DITH-sel is different to VDIG on this pin is present a 4X modulator frequency at digital level. The dither acts to span the intermodulation products present around multiple of switching frequency. Dither the modulator frequency means make it slowly changing around a nominal value. In case of a capacitor is connected to the DITH-sel pin a triangular drop is present across it and the modulator frequency value follows these behave. The maximum value reaches by it is the nominal value plus 10%, while the minimum value is nominal one minus 10%. This pick frequency values are reached when the DITH-sel pin reach the maximum voltage value. The value of capacitor is involved in the ratio of variation of modulator frequency, provided that it acts on triangular wave frequency. In case of DAC operation the modulator frequency of PWM digital out of this component is lock to the I2S input frequency, which is different from the analog modulator frequency imposed by the described oscillator. No high value intermodulation product are generated by difference of this frequency because the presence of filter between DAC out and Diff-toSE input. However a multiple frequency of DAC could be imposed to analog modulator by the CLKin-out pin. In this case no dither can be introduced. 53/64 Under voltage lock out (UVLO) TDA7572 12 Under voltage lock out (UVLO) The UVLO lock at the voltage references value used to run the device. If some of them are not in the rate band the system is put in tristate or in stand-by. The Auto-mute Voltage Setting pin (pin56) voltage is used to define the limits of this voltage references. List of monitored pin: 1. 2. 3. 4. 5. MODE0 and MODE1 voltage value VSP-VSM voltage difference SVR voltage value VSP-SVR or VSR-VSM voltage difference V14 voltage value - - - - VSP - UVLO VP2.5/VM2.5 UVLO V14 - UVLO SVR - UVLO In the UVLO could be defined four blocks: 12.1 VSP-UVLO This block monitors the VSP-VSM drop and eventually moves the modulator in mute or in tristate. The limits imposed by the VSP-UVLO block are principally three: 1. 2. 3. an adjustable limit on the minimum supply/drop an adjustable limit on the maximum supply/drop an absolute limit on the maximum supply The adjustable limits are obtained by means of the reference voltage present on the AutomuteVSetting pin, which is fixed by means of a ladder resistor of R1 and R2 between VP2.5 and SVR. The comparators that sense the voltage drop for the auto mute are provided of hysteresis. An hysteresis is still present for the auto-tristate and expressed in the spec as two different thresholds that are function of reference voltage and slope polarity. 12.2 V14 - UVLO This block monitors the V14-VSM drop voltage and eventually moves the modulator in mute or in tristate. The V14-UVLO block fixes a limit on the minimum drop. An hysteresis is present for the auto-tristate and expressed in the spec as two different thresholds that are function of slope polarity. An hysteresis is still present for the auto-mute and expressed in the spec as two different thresholds that are function of auto-tristate threshold and slope polarity. 54/64 TDA7572 Under voltage lock out (UVLO) 12.3 SVR - UVLO This block monitors the SVR-VSM drop voltage and eventually moves the modulator in tristate. The SVR-UVLO block fixes a limit on the minimum drop. An hysteresis is present for the auto-tristate and expressed in the spec as two different thresholds that are function of slope polarity. An hysteresis is still present for the auto-mute and expressed in the spec as two different thresholds that are function of auto-tristate threshold and slope polarity. 55/64 Start-up procedures, modulator turn-on after a tristate condition. TDA7572 13 Start-up procedures, modulator turn-on after a tristate condition. Start-up Condition to be respected to turn-on the modulator at the start-up: 13.1 Are MODE0 and/or MODE1 pins at voltage higher than 2.3V? Is the command "TristateMOD" Set to "1"? Is the PLL locked? (Only in case of digital Input) Is the Thermal protection FLAG ON? Are the VSP-VP2.5 and VM2.5-VSM drop voltage respectively over VAP and VAM? Is the VSP-VSM voltage lower than VU and VUC? Is the total VSP-VSM Higher than VPO+? Is the SVR pin higher than Vsvr+? Is the 14V pin supply higher than V14mute+? TristateMOD represents an internal signal which is - in NOI2CBUS MODE set to '1' when the digital supply pin VDIG (50) reaches its steady state value. - in I2C MODE set to '1' when the digital supply pin VDIG (50) reaches its steady state value and by I2C bus is written '1' on the D4 bit of modulator register. - in NOI2CDIAGNOSTIC set to '1' when the digital supply pin VDIG (50) reaches its steady state value and the turn-on diagnostic has positive result. The thermal protection represent an internal signal which is set to '1' at the start-up and eventually set to '0' if - the internal temperature trespass the second threshold and/or - the external temperature trespass the second threshold Once all the listed condition present in the above table are respected the modulator is get out from tri-state after ~500s. 13.2 Tristate When the modulator is put in tristate by some diagnostic condition the system retrieve from this condition in two possible mode depending from the supplies configuration - - split supply: The modulator starts to switch ~500s after all conditions listed in the above table are realized. Single-supply: Only in case of single supply, is activated a circuit that inhibit the startup of the SVR capacitor charge (then the modulator enable) if the SVR voltage is higher than 1.5V. If, during the normal activity of the modulator, an event that moves the modulator in tristate is present (due to, as example, an UVLO) the Vsvr gets to discharge until its value is under 1.5V. Ones reached this value the capacitor svr start to charge. The modulator starts to switch ~500s after all conditions listed in the above table are realized. Purpose of this circuit is to avoid fast turn-off/on of the modulator and increase the pop performance. 56/64 TDA7572 Applications 14 14.1 Applications Single supply Figure 12. Single supply evaluation board schematic. AC00110 57/64 Applications Figure 13. Single supply evaluation PCB TDA7572 AC00111 Top layer and component layout AC00112 Bottom layer 58/64 TDA7572 Applications 14.2 Split supply Figure 14. Split supply evaluation board schematic. AC00113 59/64 Applications Figure 15. Split supply evaluation PCB TDA7572 AC00114 Top layer and component layout AC00115 Bottom layer 60/64 TDA7572 Applications 14.3 THD+N step-up on The graph below report the THD+N vs. Pout of a TDA7572 board with step-up on and 50Hz input sine wave. Condition and step to made the board working are: 1. 2. 3. 4. 5. connect a voltage supplier to the connector J1: Positive terminal (max 14V) connected to L14V, ground terminal connected to -Vs. connect the differential input signal on INP and INM BNC input or connect the single ended input on the INP BNC and short cut the INM BNC. connect the load of 4Ohm to the connector J2. turn-on the device by means of MODE0 switch. put in play the device by operating on MUTE switch Figure 16. THD+N step-up on 61/64 Package information TDA7572 15 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 17. HiQUAD-64 mechanical data and package dimensions DIM. MIN. A A1 A2 A3 b c D D2 E e E2 E3 E4 F G L N S 0.80 2.35 9.30 13.30 9.50 13.50 0.10 0.12 1.10 0.031 10(max.) 0(min.), 7(max.) 0 2.50 0 0.22 0.23 17.00 14.00 2.80 14.00 0.65 2.65 9.70 13.70 0.092 0.366 0.523 0.374 0.531 0.004 0.005 0.043 2.65 17.00 mm TYP. MAX. 3.15 0.25 2.90 0.10 0.38 0.32 17.40 14.10 2.95 17.40 14.10 0 0.10 0 0.008 0.009 0.669 0.547 0.104 0.669 0.547 0.551 0.025 0.104 0.382 0.539 0.551 0.110 MIN. inch TYP. MAX. 0.124 0.010 0.114 0.004 0.015 0.012 0.685 0.555 0.116 0.685 0.555 OUTLINE AND MECHANICAL DATA D1 (1) 13.90 E1 (1) 13.90 (1): "D1" and "E1" do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm(0.006inch) per side HiQUAD-64 N E2 A2 c A A b BOTTOM VIEW 33 FM A B 53 e E3 D2 (slug tail width) B E1 E E3 slug (bottom side) Gauge Plane 0.35 C S L A3 SEATING PLANE G C 64 1 21 COPLANARITY E4 (slug lenght) D1 D POQU64ME A1 62/64 TDA7572 Revision history 16 Revision history Table 34. Date 3-Sep-2007 Document revision history Revision 1 Initial release. Changes 63/64 TDA7572 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 64/64 |
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